Incorporating Yield Enhancement into the Floorplanning Process

Koren and Koren : Incorporating Yield Enhancement into the Floorplanning Process

A Multi-objective Floorplanner for Shuttle Mask Optimization

Shrinkage of VLSI feature size and use of advanced Reticle Enhancement Technologies (RET) in manufacturing such as OPC and PSM have dramatically pushed up cost of mask. For example of a 130nm or 90nm mask set, the mask cost can easily reach one or two million US dollars. Shuttle mask is an effective method to share the mask cost by putting different chips on the same mask. Shuttle mask floorpla...

Constructive floorplanning with a yield objective

The ability to improve the yield of integrated circuits through layout modification has been recognized, and several techniques for yield enhanced routing and compaction have been developed. Still, yield issues are rarely a factor in the choice of the floorplan mainly due to the tendency to focus on the more important timing and area objectives. Consequently, floorplanning tools have been devel...

A damage model incorporating dynamic plastic yield surface

In this paper, a general elastoplastic-damage constitutive model considering the effect of strain rate has been developed. The derivation of this model has been cast into the irreversible thermodynamics with internal variables within the fundamentals of Continuum Damage Mechanics (CDM). The rate effect has been involved as an additional term into the plastic yield surface (dynamic plastic yield...

Yield and Routing Objectives in Floorplanning

Traditionally the oorplan of a chip has been determined so as to minimize the total chip area and reduce the routing costs. Recently, it has been shown that the oorplan also a ects the yield of the chip. Consequently, it becomes desirable to consider the expected yield, in addition to the cost of routing, when selecting a oorplan. The goal of this paper is to study the two seemingly disjoint ob...